무어(Moore)의 법칙은 느려지는데 클라우드 데이터 센터의 성능 요구는 지속적으로 증가함.

​CPU 개발자들은 설정되어 있는 비용의 제약에 직면함과 동시에 소켓 당 최대 성능을 제공하기 위해 설계를 고심하고 있음. 

세미 어널리시스(Semi Analysis)에 따르면 암드의 에픽 '베르가모' 는 젠 4와 본질적으로 동일한 기능 묶음을 유지하​는 미세 구조로써

​특수한 맞춤형 젠 4c 미세 구조를 기반으로 ​코어 크기 요구 사항을 절반으로 줄이는 ​업계 최초의 x86 클라우드 네이티브 CPU.

96 코어 에픽 '제노아' CPU 와 동일한 소켓 SP5에 장착되는 에픽 '베르가모' 프로세서는 128개의 코어를 장착하며  

제노아와 유사한 12채널 DDR5-4800 메모리 서브 시스템과 동일한 I/O 다이(코드명 플로이드)를 사용.

128개의 PCIe Gen5 레인 및 기타 SP5 제품의 특성도 갖추고 있음. 

클라우드 네이티브 시스템 온 칩(SoC)인 베르가모의 설계는 암페어, 아마존, 구글 및 마소의 새로운 Arm 기반 데이터 센터 등급 SoC 에 

어느 정도 대응하므로 효율성, 전력 사용량, 다이 크기, 코어 당 최대 성능을 제공하는 것 뿐만 아니라 

낮은 총 소유 비용(TCO)을 제공.

On the microarchitecture level, Zen 4c retains the same design as Zen 4, including identical features and instructions-per-clock-performance, but they are configured and implemented in a drastically different way, SemiAnalysis claims.  When it comes to Zen 4c 'Dionysus' cores, they are about 35.4% smaller compared to Zen 4 'Persephone' cores, according to SemiAnalysis. To achieve this, AMD had to implement a number of design tricks. The analysts believe: 

• It reduced boost clock targets from 3.70 GHz to 3.10 GHz. This made timing closure simpler and decreased the need for extra buffer cells to meet relaxed timing constraints. Today's designs are often constrained by routing density and congestion, so lowering  frequency allows for tighter packing of signal pathways, enhancing the density of standard cells.
• It lowered the number of physical partitions of a die and packed logic closer together, which made debugging and introducing fixes harder but reduced die size.
• It used denser 6T dual-port SRAM cells for Zen 4c as opposed to 8T dual-port SRAM circuits for Zen 4 to reduce SRAM area. As a result, while Zen 4 and Zen 4c cores have similar L1 and L2 cache sizes, the area used by caches in case of Zen 4c is lower, but these caches also are not as fast as those inside Zen 4. 
• Finally, it removed through-silicon vias (TSVs) arrays for 3D V-Cache, to further save silicon. 

These were not the only methods of die area reduction used by AMD. According to SemiAnalysis, AMD's Bergamo is based on eight Vindhya core complex dies (CCDs) that pack 16 Zen 4c cores (up from eight Zen 4 cores per CCD) — which is justified as cores got smaller, but which also impacts clock speed potential. Each CCD also features two eight-core core complexes (CCX) and 32MB of L3 cache, or 16MB per CCX. By contrast, each Zen 4 CCX has 32MB of L2, which greatly increases its size compared to Zen 4c CCX. 

Overall, we could say that AMD's Zen 4c and Bergamo make design trajectory shift as the company needed to fit 128 Zen 4-class cores into the same 360W – 400W power envelope as Genoa. Reduced frequency targets, usage of denser SRAM cells, and cutting L3 per CCX in half certainly enabled AMD to increase its core count, but how that impacted per-core performance is something that we will still have to find out.

SemiAnalysis says that AMD is preparing to launch two Bergamo processors later this month: the 128-core EPYC 9754 and its slightly cut-down sibling, the 112-core EPYC 9734. Given that operators of exascale datacenters tend to have specific requirements for their deployments, we can only wonder how many custom and semi-custom Bergamo offerings AMD will eventuall produce, but for now two models are set to be introduced already next week.