TSMC 회장은 AI 칩이 부족한 게 아니라 이를 패키징할 고급 기술인 CoWoS의 처리 용량이 부족하다면서, 패키징 시설을 확장해서 물량을 소화하려면 1년 반 정도가 걸린다고 밝혔습니다. 

https://asia.nikkei.com/Business/Tech/Semiconductors/TSMC-sees-AI-chip-output-constraints-lasting-1.5-years

TSMC sees AI chip output constraints lasting 1.5 years

TAIPEI -- Supply constraints on AI chips will take about 18 months to ease, the world's largest contract chipmaker said on Wednesday, as companies continue to snap up the advanced processors needed to power generative artificial intelligence applications like ChatGPT.

Taiwan Semiconductor Manufacturing Co. Chairman Mark Liu said the squeeze on AI chip supplies is "temporary" and could be alleviated by the end of 2024.

TSMC is the sole manufacturer for Nvidia's powerful H100 and A100 AI processors, the hardware that powers AI tools like ChatGPT and which are also used in the majority of AI data centers.

Liu explained that the supply constraints are due not to a lack of physical chips but to limited capacity in advanced chip packaging services, a key step in the manufacturing process.

"It's not the shortage of AI chips. It's the shortage of our COWOS [advanced chip packaging] capacity," Liu said on the sidelines of the SEMICON Taiwan industry fair. Demand for COWOS picked up "suddenly," he said, tripling in a year.

"Currently, we can't fulfill 100% of our customers' needs, but we try to support about 80%. We think this is a temporary phenomenon. After our expansion of [advanced chip packaging capacity], it should be alleviated in one and a half years."

COWOS is an advanced chip packaging technique developed by TSMC to connect different types of chips together. The process combines a graphic processor unit (GPU) with six high-bandwidth memory chips to enable high-speed data transmission and the overall performance needed to train large language models for use in AI.

Nvidia's A100 and H100 series are made with TSMC's COWOS process.

TSMC recently announced plans to build a $2.9 billion facility for advanced chip packaging in Miaoli, Taiwan, to meet the growing AI demand.

Liu's comments on the bottleneck in AI chip output underscore the importance of advanced chip packaging and stacking technologies in the race to produce more powerful and efficient semiconductors.

Traditional cutting-edge chip manufacturing aims to squeeze as many transistors onto one tiny chip as possible, but thanks to advances in chip packaging, this is not the only way to increase computing power.

Liu said that to meet the surging demand for AI products, the semiconductor industry should embrace a "paradigm shift" of new ways to connect, package and stack chips.

"We are now putting together many chips into a tightly integrated massive interconnect system. This is a paradigm shift in semiconductor technology integration," Liu said.

The chairman said today's premium AI accelerators have about 100 billion transistors. To place even more transistors on a system quickly will require "interconnecting multiple chips to provide 2.5D or 3D integration."

TSMC forecasts that within the next 10 years, there will be chips with more than 1 trillion transistors. More transistors generally means more computing power.

"It's through packaging with multiple chips that this could be possible," Liu said.

Advanced chip packaging has already emerged as a key battleground for top chipmakers like Intel, Samsung and TSMC in the race to produce ever more powerful chips.

Intel also aims to quadruple capacity for its most advanced chip packaging capacity by 2025, as America's biggest chipmaker seeks to regain the global lead in semiconductor manufacturing.