🗨️ PCI-SIG 협회, '차세대 PCI-익스프레스' 보조전원 규격인 'Copper-Link'를 개발 발표
▶ PCI-SIG 협회, Super-Computer 2023(SC23) 컨퍼런스에서 '차세대 PCI-익스프레스 보조전원 규격'을 개발 발표
- 신규 보조전원 규격 이름 : Copper-Link(구리-링크) ☞ 단순히 직역입니다.
- 신규 보조전원 규격의 출시 예정년도 : 2024년 목표
- 추가 개발중 : PCI-익스프레스의 '5.0 및 6.0' 내부 & 외부 케이블 사양
- 참여 회사 : Astera Labs, Dolphin Interconnect Solutions, Synopsys, Tektronix
※ 현재는 '신규 보조전원 규격'의 개발만 공개하였음.(아직 구체적 정보는 공유되지 않았음)
※ 비슷한 이름 존재함 : 'Patton Electronics' 회사의 'CopperLink 이더넷 케이블'
(CopprLink는 스타일이나 기타 세부 사항을 공개하기 위한 USPTO 상표 검색에 나타나지도 않음)
PCI-SI Highlights PCIe Technology as the Interconnect of Choice for HPC at SC23
Members showcasing PCIe technology demos and new PCI Express Cable naming scheme announced
PCI-SIG announced the new naming scheme for PCIe Internal and External Cables will be CopprLink. The PCIe 5.0 and PCIe 6.0 Internal and External Cable Specifications are currently in development and are targeted for release in 2024.
View the PCIe technology demos at SC23
WHEN: Monday, November 13 – Thursday, November 16, 2023
WHERE: SC23 – Colorado Convention Center, Denver, CO • PCI-SIG Booth #1401
WHO: Members of PCI-SIG, the consortium that owns and manages PCI specification as open industry standards, will be showcasing PCI Express (PCIe) technology demonstrations at SC23 in booth #1401.
WHAT: PCI-SIG invites SC23 attendees to visit booth #1401 to view the demos and learn more about the PCIe technology ecosystem. The demonstrations highlight the role of PCIe technology as the high-speed I/O interconnect of choice for High-Performance Computing (HPC) applications. The participating companies include Astera Labs, Dolphin Interconnect Solutions, Synopsys, and Tektronix.
The demonstration highlights HPC applications so CopprLink should target the interface solutions as we are likely looking at interface cables rather than power cables to deliver optimal transfer bandwidth to various devices onboard next-gen platforms. The PCIe 6.0 platform will mark a doubling of transfer rates from 32 GT/s (Gen 5.0) to 64 GT/s (Gen 6.0). The new standard is also expected to deliver up to 256 GB/s of bandwidth across a x16 lane link.
In any case, if CopprLink is related to the power interface cables, then the company will try to fix some of the issues it encountered when designing the current 12VHPWR Gen 5.0 standard. Although the design was gradually optimized with the release of the 12V-2x6 standard, there still seems to be room for improvement, especially when thinking of future PCIe Gen 6.0 hardware.
But before we dive more into that side, it should be clarified once again that this announcement is specifically for interface cables that provide PCIe interlink over various ports. Expect more details on CopprLink PCIe Gen 5.0 and Gen 6.0 cables in the coming months.
https://wccftech.com/pci-sig-confirms-pcie-gen-5-0-gen-6-0-use-new-copprlink-cables/
